Battery metrics; DRAM training modes; imaging innovation in AR/VR; electric motor efficiency.
Ansys’ Vidyu Challa checks out how to identify the most important battery metrics for a particular application and trade these off against others with a focus on the important considerations when selecting the right battery for a consumer application, such as rechargeability, energy density, power density, shelf life, safety, form factor, cost, and flexibility.
Cadence’s Shyam Sharma points to the Training Modes supported by the latest DRAMs that assist with handshaking for high speed I/O and what system designers ought to consider for systems to work as intended, including ensuring initiator and target are able to communicate with each other.
Synopsys’ Emilie Viasnoff examines how AR/VR is driving innovation in imaging design and why the same level of effort that goes into packing incredible amounts of compute performance into smartphones must be deployed by optics-electronics community to enable miniaturized, digital, and smart imaging systems.
Siemens’ Adrian Perregaux and Jonathan Melvin find that to significantly reduce global electricity use, increasing the efficiency of electric motors is key and that electromagnetic simulation can help in the design of more efficient motors.
Arm’s Chris Bergey argues that the core elements of computing need to be rethought to combat increasing energy consumption and associated carbon emissions and calls for new processor designs, new server architectures, and other disruptive approaches.
Coventor’s Jeonghoon Kim looks at how building and sharing sets of process libraries not only increases the process expertise available within a company but also leads to more accurate process modeling and faster time to market.
Codasip’s Philippe Luc suggests taking a ‘Swiss cheese model’ approach to processor verification by layering many different verification techniques to create a redundancy that has a higher chance of catching bugs than any one strategy alone.
Lam Research’s David Haynes checks out how 5G and Wi-Fi 6/6E can work together to create a seamless, integrated wireless experience by handing off mobile data from 5G networks to Wi-Fi as people move through daily environments.
SEMI’s Inna Skvortsova considers how the digital transformation of global economies led to 2021 marking a second consecutive year of record growth for the semiconductor industry despite the turbulence brought by COVID-19, geopolitical tensions, and supply-chain constraints.
Nvidia’s Arash Vahdat and Karsten Kreis explain how generative adversarial networks are used to synthesize novel data and images based on real data, the three key requirements of generative models that are difficult to satisfy simultaneously, and a class called diffusion models that show promise for high sample quality and mode coverage.
Memory analyst Jim Handy examines the chip shortage’s impact on pricing trends and how it interacts with memory demand, growth, and availability.
And don’t miss the blogs featured in the recent Automotive, Security, & Pervasive Computing and Test, Measurement & Analytics newsletters:
Rambus’ Rocky Zhang explains how to protect data in memory even if isolation techniques are compromised.
Arteris IP’s Paul Graykowski looks at further optimization of RTL repartitioning when switching from crossbar interconnects to NoCs.
Siemens’ Lance Brooks and Brendan Morris examine why the complex E/E architecture of modern vehicles makes network design and software development daunting.
Synopsys’ Gordon Cooper digs into accelerating math intensive neural networks while remaining area efficient and programmable.
Tortuga Logic’s Melissa Jordan warns that a security-first approach isn’t always enough to ensure comprehensive protection from hardware weaknesses.
AMD’s Subh Bhattacharya explores implementing very high data rate algorithms using adaptive computing architectures.
Cadence’s Veena Parthan focuses on overset meshing to capture regions of fluid-structure interactions and turbulence for helicopter design.
Onto’s Johnny Dai breaks down how to measure multi-layer metal stacks of repeating metal films in the RF filter process flow for 5G.
Synopsys’ Ash Patel advises monitoring how process variation and aging affect timing of actual chips in real-world deployment.
Advantest’s Ken Butler explains why using data analytics can keep the cost of test at reasonable levels without compromising quality or reliability.
Siemens’ Richard Oxland finds that traditional software-only security measures aren’t enough to meet emerging security goals.
Teradyne’s Rick Burns looks at how next-generation devices with transistor counts in the hundreds of billions will be tested.
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Disaggregation and the wind-down of Moore’s Law have changed everything.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Smart software finds more EUV stochastic defects and missing vias, improving wafer yield.
Continued expansion in new and existing markets points to massive and sustained growth.
Some of the less common considerations for assessing the suitability of a system for high-performance workloads.
Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.
Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
Hybrid bonding opens up whole new level of performance in packaging, but it’s not the only improvement.
Is there room for an even smaller version of a RISC-V processor that could replace 8-bit microcontrollers?
Why this is becoming a bigger issue, and what can be done to mitigate the effects.
Some 300mm tools are converted to 200mm; equipment prices and chip manufacturing costs are rising.
From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.
How much do we pay for a system to be programmable? It depends upon who you ask.